SDDL=000, DLCS=0, TMOH=0, TMOL=0, TMOS=0
I2C Bus Mode Register 2
| TMOS | Timeout Detection Time Selection 0 (0): Long mode is selected. 1 (1): Short mode is selected. |
| TMOL | Timeout L Count Control 0 (0): Count is disabled while the SCLn line is at a low level. 1 (1): Count is enabled while the SCLn line is at a low level. |
| TMOH | Timeout H Count Control 0 (0): Count is disabled while the SCLn line is at a high level. 1 (1): Count is enabled while the SCLn line is at a high level. |
| Reserved | This bit is read as 0. The write value should be 0. |
| SDDL | SDA Output Delay Counter 0 (000): No output delay 1 (001): 1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles (ICMR2.DLCS=1) 2 (010): 2 fIIC cycles (ICMR2.DLCS=0) / 3 or 4 fIIC cycles (ICMR2.DLCS=1) 3 (011): 3 fIIC cycles (ICMR2.DLCS=0) / 5 or 6 fIIC cycles (ICMR2.DLCS=1) 4 (100): 4 fIIC cycles (ICMR2.DLCS=0) / 7 or 8 fIIC cycles (ICMR2.DLCS=1) 5 (101): 5 fIIC cycles (ICMR2.DLCS=0) / 9 or 10 fIIC cycles (ICMR2.DLCS=1) 6 (110): 6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1) 7 (111): 7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1) |
| DLCS | SDA Output Delay Clock Source Selection 0 (0): The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter. 1 (1): The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter. |